


ARM Macro Assembler    Page 1 


    1 00000000         ;/*
    2 00000000         ; * Copyright (c) 2006-2018, RT-Thread Development Team
    3 00000000         ; *
    4 00000000         ; * SPDX-License-Identifier: Apache-2.0
    5 00000000         ; *
    6 00000000         ; * Change Logs:
    7 00000000         ; * Date           Author       Notes
    8 00000000         ; * 2009-01-17     Bernard      first version
    9 00000000         ; * 2013-06-18     aozima       add restore MSP feature.
                       
   10 00000000         ; * 2013-07-09     aozima       enhancement hard fault e
                       xception handler.
   11 00000000         ; */
   12 00000000         
   13 00000000         ;/**
   14 00000000         ; * @addtogroup CORTEX-M3
   15 00000000         ; */
   16 00000000         ;/*@{*/
   17 00000000         
   18 00000000 E000ED08 
                       SCB_VTOR
                               EQU              0xE000ED08  ; Vector Table Offs
                                                            et Register
   19 00000000 E000ED04 
                       NVIC_INT_CTRL
                               EQU              0xE000ED04  ; interrupt control
                                                             state register
   20 00000000 E000ED20 
                       NVIC_SYSPRI2
                               EQU              0xE000ED20  ; system priority r
                                                            egister (2)
   21 00000000 00FF0000 
                       NVIC_PENDSV_PRI
                               EQU              0x00FF0000  ; PendSV priority v
                                                            alue (lowest)
   22 00000000 10000000 
                       NVIC_PENDSVSET
                               EQU              0x10000000  ; value to trigger 
                                                            PendSV exception
   23 00000000         
   24 00000000                 AREA             |.text|, CODE, READONLY, ALIGN=
2
   25 00000000                 THUMB
   26 00000000                 REQUIRE8
   27 00000000                 PRESERVE8
   28 00000000         
   29 00000000                 IMPORT           rt_thread_switch_interrupt_flag
   30 00000000                 IMPORT           rt_interrupt_from_thread
   31 00000000                 IMPORT           rt_interrupt_to_thread
   32 00000000         
   33 00000000         ;/*
   34 00000000         ; * rt_base_t rt_hw_interrupt_disable();
   35 00000000         ; */
   36 00000000         rt_hw_interrupt_disable
                               PROC
   37 00000000                 EXPORT           rt_hw_interrupt_disable
   38 00000000 F3EF 8010       MRS              r0, PRIMASK
   39 00000004 B672            CPSID            I
   40 00000006 4770            BX               LR



ARM Macro Assembler    Page 2 


   41 00000008                 ENDP
   42 00000008         
   43 00000008         ;/*
   44 00000008         ; * void rt_hw_interrupt_enable(rt_base_t level);
   45 00000008         ; */
   46 00000008         rt_hw_interrupt_enable
                               PROC
   47 00000008                 EXPORT           rt_hw_interrupt_enable
   48 00000008 F380 8810       MSR              PRIMASK, r0
   49 0000000C 4770            BX               LR
   50 0000000E                 ENDP
   51 0000000E         
   52 0000000E         ;/*
   53 0000000E         ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 
                       to);
   54 0000000E         ; * r0 --> from
   55 0000000E         ; * r1 --> to
   56 0000000E         ; */
   57 0000000E         rt_hw_context_switch_interrupt
   58 0000000E                 EXPORT           rt_hw_context_switch_interrupt
   59 0000000E         rt_hw_context_switch
                               PROC
   60 0000000E                 EXPORT           rt_hw_context_switch
   61 0000000E         
   62 0000000E         ; set rt_thread_switch_interrupt_flag to 1
   63 0000000E 4A33            LDR              r2, =rt_thread_switch_interrupt
_flag
   64 00000010 6813            LDR              r3, [r2]
   65 00000012 2B01            CMP              r3, #1
   66 00000014 D004            BEQ              _reswitch
   67 00000016 F04F 0301       MOV              r3, #1
   68 0000001A 6013            STR              r3, [r2]
   69 0000001C         
   70 0000001C 4A30            LDR              r2, =rt_interrupt_from_thread ;
                                                             set rt_interrupt_f
                                                            rom_thread
   71 0000001E 6010            STR              r0, [r2]
   72 00000020         
   73 00000020         _reswitch
   74 00000020 4A30            LDR              r2, =rt_interrupt_to_thread ; s
                                                            et rt_interrupt_to_
                                                            thread
   75 00000022 6011            STR              r1, [r2]
   76 00000024         
   77 00000024 4830            LDR              r0, =NVIC_INT_CTRL ; trigger th
                                                            e PendSV exception 
                                                            (causes context swi
                                                            tch)
   78 00000026 F04F 5180       LDR              r1, =NVIC_PENDSVSET
   79 0000002A 6001            STR              r1, [r0]
   80 0000002C 4770            BX               LR
   81 0000002E                 ENDP
   82 0000002E         
   83 0000002E         ; r0 --> switch from thread stack
   84 0000002E         ; r1 --> switch to thread stack
   85 0000002E         ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from
                       ] stack
   86 0000002E         PendSV_Handler
                               PROC



ARM Macro Assembler    Page 3 


   87 0000002E                 EXPORT           PendSV_Handler
   88 0000002E         
   89 0000002E         ; disable interrupt to protect context switch
   90 0000002E F3EF 8210       MRS              r2, PRIMASK
   91 00000032 B672            CPSID            I
   92 00000034         
   93 00000034         ; get rt_thread_switch_interrupt_flag
   94 00000034 4829            LDR              r0, =rt_thread_switch_interrupt
_flag
   95 00000036 6801            LDR              r1, [r0]
   96 00000038 B191            CBZ              r1, pendsv_exit ; pendsv alread
                                                            y handled
   97 0000003A         
   98 0000003A         ; clear rt_thread_switch_interrupt_flag to 0
   99 0000003A F04F 0100       MOV              r1, #0x00
  100 0000003E 6001            STR              r1, [r0]
  101 00000040         
  102 00000040 4827            LDR              r0, =rt_interrupt_from_thread
  103 00000042 6801            LDR              r1, [r0]
  104 00000044 B129            CBZ              r1, switch_to_thread ; skip reg
                                                            ister save at the f
                                                            irst time
  105 00000046         
  106 00000046 F3EF 8109       MRS              r1, psp     ; get from thread s
                                                            tack pointer
  107 0000004A E921 0FF0       STMFD            r1!, {r4 - r11} ; push r4 - r11
                                                             register
  108 0000004E 6800            LDR              r0, [r0]
  109 00000050 6001            STR              r1, [r0]    ; update from threa
                                                            d stack pointer
  110 00000052         
  111 00000052         switch_to_thread
  112 00000052 4924            LDR              r1, =rt_interrupt_to_thread
  113 00000054 6809            LDR              r1, [r1]
  114 00000056 6809            LDR              r1, [r1]    ; load thread stack
                                                             pointer
  115 00000058         
  116 00000058 E8B1 0FF0       LDMFD            r1!, {r4 - r11} ; pop r4 - r11 
                                                            register
  117 0000005C F381 8809       MSR              psp, r1     ; update stack poin
                                                            ter
  118 00000060         
  119 00000060         pendsv_exit
  120 00000060         ; restore interrupt
  121 00000060 F382 8810       MSR              PRIMASK, r2
  122 00000064         
  123 00000064 F04E 0E04       ORR              lr, lr, #0x04
  124 00000068 4770            BX               lr
  125 0000006A                 ENDP
  126 0000006A         
  127 0000006A         ;/*
  128 0000006A         ; * void rt_hw_context_switch_to(rt_uint32 to);
  129 0000006A         ; * r0 --> to
  130 0000006A         ; * this fucntion is used to perform the first thread sw
                       itch
  131 0000006A         ; */
  132 0000006A         rt_hw_context_switch_to
                               PROC
  133 0000006A                 EXPORT           rt_hw_context_switch_to



ARM Macro Assembler    Page 4 


  134 0000006A         ; set to thread
  135 0000006A 491E            LDR              r1, =rt_interrupt_to_thread
  136 0000006C 6008            STR              r0, [r1]
  137 0000006E         
  138 0000006E         ; set from thread to 0
  139 0000006E 491C            LDR              r1, =rt_interrupt_from_thread
  140 00000070 F04F 0000       MOV              r0, #0x0
  141 00000074 6008            STR              r0, [r1]
  142 00000076         
  143 00000076         ; set interrupt flag to 1
  144 00000076 4919            LDR              r1, =rt_thread_switch_interrupt
_flag
  145 00000078 F04F 0001       MOV              r0, #1
  146 0000007C 6008            STR              r0, [r1]
  147 0000007E         
  148 0000007E         ; set the PendSV exception priority
  149 0000007E 481B            LDR              r0, =NVIC_SYSPRI2
  150 00000080 F44F 017F       LDR              r1, =NVIC_PENDSV_PRI
  151 00000084 F8D0 2000       LDR.W            r2, [r0,#0x00] ; read
  152 00000088 EA41 0102       ORR              r1,r1,r2    ; modify
  153 0000008C 6001            STR              r1, [r0]    ; write-back
  154 0000008E         
  155 0000008E         ; trigger the PendSV exception (causes context switch)
  156 0000008E 4816            LDR              r0, =NVIC_INT_CTRL
  157 00000090 F04F 5180       LDR              r1, =NVIC_PENDSVSET
  158 00000094 6001            STR              r1, [r0]
  159 00000096         
  160 00000096         ; restore MSP
  161 00000096 4816            LDR              r0, =SCB_VTOR
  162 00000098 6800            LDR              r0, [r0]
  163 0000009A 6800            LDR              r0, [r0]
  164 0000009C F380 8808       MSR              msp, r0
  165 000000A0         
  166 000000A0         ; enable interrupts at processor level
  167 000000A0 B661            CPSIE            F
  168 000000A2 B662            CPSIE            I
  169 000000A4         
  170 000000A4         ; never reach here!
  171 000000A4                 ENDP
  172 000000A4         
  173 000000A4         ; compatible with old version
  174 000000A4         rt_hw_interrupt_thread_switch
                               PROC
  175 000000A4                 EXPORT           rt_hw_interrupt_thread_switch
  176 000000A4 4770            BX               lr
  177 000000A6                 ENDP
  178 000000A6         
  179 000000A6                 IMPORT           rt_hw_hard_fault_exception
  180 000000A6                 EXPORT           HardFault_Handler
  181 000000A6         HardFault_Handler
                               PROC
  182 000000A6         
  183 000000A6         ; get current context
  184 000000A6 F01E 0F04       TST              lr, #0x04   ; if(!EXC_RETURN[2]
                                                            )
  185 000000AA BF0C            ITE              EQ
  186 000000AC F3EF 8008       MRSEQ            r0, msp     ; [2]=0 ==> Z=1, ge
                                                            t fault context fro
                                                            m handler.



ARM Macro Assembler    Page 5 


  187 000000B0 F3EF 8009       MRSNE            r0, psp     ; [2]=1 ==> Z=0, ge
                                                            t fault context fro
                                                            m thread.
  188 000000B4         
  189 000000B4 E920 0FF0       STMFD            r0!, {r4 - r11} ; push r4 - r11
                                                             register
  190 000000B8 F840 ED04       STMFD            r0!, {lr}   ; push exec_return 
                                                            register
  191 000000BC         
  192 000000BC F01E 0F04       TST              lr, #0x04   ; if(!EXC_RETURN[2]
                                                            )
  193 000000C0 BF0C            ITE              EQ
  194 000000C2 F380 8808       MSREQ            msp, r0     ; [2]=0 ==> Z=1, up
                                                            date stack pointer 
                                                            to MSP.
  195 000000C6 F380 8809       MSRNE            psp, r0     ; [2]=1 ==> Z=0, up
                                                            date stack pointer 
                                                            to PSP.
  196 000000CA         
  197 000000CA B500            PUSH             {lr}
  198 000000CC F7FF FFFE       BL               rt_hw_hard_fault_exception
  199 000000D0 F85D EB04       POP              {lr}
  200 000000D4         
  201 000000D4 F04E 0E04       ORR              lr, lr, #0x04
  202 000000D8 4770            BX               lr
  203 000000DA                 ENDP
  204 000000DA         
  205 000000DA 00 00           ALIGN            4
  206 000000DC         
  207 000000DC                 END
              00000000 
              00000000 
              00000000 
              E000ED04 
              E000ED20 
              E000ED08 
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
ork --depend=test\context_rvds.d -otest\context_rvds.o -I.\RTE\RTOS -I.\RTE\_te
st -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include -IC:\Keil_v5\ARM\PACK\Ke
il\STM32F1xx_DFP\2.1.0\Device\Include -IC:\Keil_v5\ARM\PACK\RealThread\RT-Threa
d\3.1.3\components\finsh -IC:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\inclu
de --predefine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 524" --p
redefine="_RTE_ SETA 1" --predefine="STM32F10X_HD SETA 1" --list=context_rvds.l
st C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\arm\cortex-m3\context_
rvds.S



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.text 00000000

Symbol: .text
   Definitions
      At line 24 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      None
Comment: .text unused
HardFault_Handler 000000A6

Symbol: HardFault_Handler
   Definitions
      At line 181 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
   Uses
      At line 180 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
Comment: HardFault_Handler used once
PendSV_Handler 0000002E

Symbol: PendSV_Handler
   Definitions
      At line 86 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 87 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
Comment: PendSV_Handler used once
_reswitch 00000020

Symbol: _reswitch
   Definitions
      At line 73 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 66 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
Comment: _reswitch used once
pendsv_exit 00000060

Symbol: pendsv_exit
   Definitions
      At line 119 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
   Uses
      At line 96 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
Comment: pendsv_exit used once
rt_hw_context_switch 0000000E

Symbol: rt_hw_context_switch
   Definitions
      At line 59 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 60 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
Comment: rt_hw_context_switch used once



ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Relocatable symbols

rt_hw_context_switch_interrupt 0000000E

Symbol: rt_hw_context_switch_interrupt
   Definitions
      At line 57 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 58 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
Comment: rt_hw_context_switch_interrupt used once
rt_hw_context_switch_to 0000006A

Symbol: rt_hw_context_switch_to
   Definitions
      At line 132 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
   Uses
      At line 133 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
Comment: rt_hw_context_switch_to used once
rt_hw_interrupt_disable 00000000

Symbol: rt_hw_interrupt_disable
   Definitions
      At line 36 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 37 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
Comment: rt_hw_interrupt_disable used once
rt_hw_interrupt_enable 00000008

Symbol: rt_hw_interrupt_enable
   Definitions
      At line 46 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 47 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
Comment: rt_hw_interrupt_enable used once
rt_hw_interrupt_thread_switch 000000A4

Symbol: rt_hw_interrupt_thread_switch
   Definitions
      At line 174 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
   Uses
      At line 175 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
Comment: rt_hw_interrupt_thread_switch used once
switch_to_thread 00000052

Symbol: switch_to_thread
   Definitions
      At line 111 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
   Uses
      At line 104 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S



ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Relocatable symbols

Comment: switch_to_thread used once
12 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Absolute symbols

NVIC_INT_CTRL E000ED04

Symbol: NVIC_INT_CTRL
   Definitions
      At line 19 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 77 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
      At line 156 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S

NVIC_PENDSVSET 10000000

Symbol: NVIC_PENDSVSET
   Definitions
      At line 22 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 78 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
      At line 157 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S

NVIC_PENDSV_PRI 00FF0000

Symbol: NVIC_PENDSV_PRI
   Definitions
      At line 21 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 150 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
Comment: NVIC_PENDSV_PRI used once
NVIC_SYSPRI2 E000ED20

Symbol: NVIC_SYSPRI2
   Definitions
      At line 20 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 149 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
Comment: NVIC_SYSPRI2 used once
SCB_VTOR E000ED08

Symbol: SCB_VTOR
   Definitions
      At line 18 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 161 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
Comment: SCB_VTOR used once
5 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
External symbols

rt_hw_hard_fault_exception 00000000

Symbol: rt_hw_hard_fault_exception
   Definitions
      At line 179 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
   Uses
      At line 198 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
Comment: rt_hw_hard_fault_exception used once
rt_interrupt_from_thread 00000000

Symbol: rt_interrupt_from_thread
   Definitions
      At line 30 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 70 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
      At line 102 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
      At line 139 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S

rt_interrupt_to_thread 00000000

Symbol: rt_interrupt_to_thread
   Definitions
      At line 31 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 74 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
      At line 112 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S
      At line 135 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S

rt_thread_switch_interrupt_flag 00000000

Symbol: rt_thread_switch_interrupt_flag
   Definitions
      At line 29 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
   Uses
      At line 63 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
      At line 94 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu\
arm\cortex-m3\context_rvds.S
      At line 144 in file C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\libcpu
\arm\cortex-m3\context_rvds.S

4 symbols
357 symbols in table
